File:Verilog Simple Assignment.svg

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Verilog_Simple_Assignment.svg‎ (SVG file, nominally 125 × 70 pixels, file size: 10 KB)
Description
English: A simple assignment in Verilog 
wire a, b, c;
assign a = b & c;
Date

23 May 2009(2009-05-23)
Source

Own work
Author

Inductiveload
Permission
(Reusing this file)
Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
In some countries this may not be legally possible; if so:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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Date/TimeThumbnailDimensionsUserComment
current00:34, 23 May 2009Thumbnail for version as of 00:34, 23 May 2009125 × 70 (10 KB)Inductiveload ({{Information |Description={{en|1=A simple assignment in Verilog wire a, b, c; assign a = b & c;}} |Source=Own work by uploader |Author=Inductiveload |Date=2009/05/23 |Permission={{PD-self}} |other_versions= }} <!--{{ImageUpload)

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Metadata

This file contains additional information, probably added from the digital camera or scanner used to create or digitize it. If the file has been modified from its original state, some details may not fully reflect the modified file.
Width 125
Height 70
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