This is a file from the Wikimedia Commons

File:Verilog Simple Assignment.svg

From Wikibooks, open books for an open world
Jump to navigation Jump to search

Original file ‎(SVG file, nominally 125 × 70 pixels, file size: 10 KB)

Description
English: A simple assignment in Verilog 
wire a, b, c;
assign a = b & c;
Date
Source Own work
Author Inductiveload
Permission
(Reusing this file)
Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
In some countries this may not be legally possible; if so:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

Captions

Add a one-line explanation of what this file represents

Items portrayed in this file

depicts

inception

23 May 2009

File history

Click on a date/time to view the file as it appeared at that time.

Date/TimeThumbnailDimensionsUserComment
current00:34, 23 May 2009Thumbnail for version as of 00:34, 23 May 2009125 × 70 (10 KB)Inductiveload{{Information |Description={{en|1=A simple assignment in Verilog wire a, b, c; assign a = b & c;}} |Source=Own work by uploader |Author=Inductiveload |Date=2009/05/23 |Permission={{PD-self}} |other_versions= }} <!--{{ImageUpload

The following page uses this file:

Retrieved from "https://en.wikibooks.org/wiki/File:Verilog_Simple_Assignment.svg"