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File:CMOS OR.svg

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Original file ‎(SVG file, nominally 375 × 250 pixels, file size: 4 KB)

Summary

Description Layout of NMOS and PMOS components in an OR Gate. This OR gate is implemented as an AND gate with both inputs inverted(by using PMOS at the top) as well as the output (inverter at the right) which is functionally correct, but is not commonly used as it requires 2 extra transistors.
Date
Source Own work using: Inkscape 0.43
Author inductiveload
SVG development
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The SVG code is valid.
 
This circuit diagram was created with Inkscape.

Licensing

Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
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inception

12 July 2006

MIME type

image/svg+xml

checksum

2ac5c0cd9f4d75d5b703c0e944ed1991659938c2

determination method: SHA-1

data size

4,161 byte

height

250 pixel

width

375 pixel

File history

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Date/TimeThumbnailDimensionsUserComment
current18:24, 21 January 2020Thumbnail for version as of 18:24, 21 January 2020375 × 250 (4 KB)GKFXUse <text> rather than text as path to give better thumbnails
19:25, 24 March 2014Thumbnail for version as of 19:25, 24 March 2014375 × 250 (21 KB)Wereldburger758Valid SVG now.
19:40, 12 July 2006Thumbnail for version as of 19:40, 12 July 2006375 × 250 (29 KB)Inductiveload{{Information |Description=Layout of NMOS and PMOS components in an OR Gate |Source=Own drawing, Inkscape 0.43 |Date=12/07/06 |Author=inductiveload |Permission=PD |other_versions= }} Category:CMOS

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