Digital Circuits/Optimization

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[edit] Similar States

[edit] Coloring

[edit] State Minimization

While a correctly-designed state machines has an unambiguous behaviour, there can be more than one way on implementing that same behaviour. Conder the two FSMs below:

FSM Odd Parity Detector.svg

Generally speaking, we want to find the implementation of an FSM which have fewest state, and therefore require fewest resources, be this size of a ROM device or LEs in an FPGA.

[edit] Implication Charts

Implication charts are a common way of reducing an FSM. It works by finding states that have identical transitions to each other. It is a graphical method suitable for fast computation by hand.

First, lets consider a grid of size N×N, where N is the number of states. Each cell represents a pair of states. As this is an unordered pair, the cell (i, j) is equivalent to (j,i), so it can be omitted (green squares). Also, the state is of course equivalent to itself (blue squares). We can then eliminate the upper right triangle and the diagonal. For a seven-state machine, we will have the following implication chart outline:

Implication Chart Setup.svg

Note that there are N−1 squares in each direction, and that in any cell, M<N.

In order to begin optimising an FSM, we need a state transition table. For this example, we will take as an example the FSM that implements the following:

Current State Next State Output
Input X Input X
0 1 0 1
0 7 2 0 0
1 7 5 0 0
2 7 0 1 0
3 0 7 1 0
4 3 6 0 0
5 3 1 1 0
6 3 4 1 0
7 4 3 1 0