Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The error function
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[edit] Error function of the second order slave CDR
Another way of looking at the same critical frequency band of PLL tracking, seen in the previous section about the jitter transfer function, is to look at the function that describes the phase difference between output and input.
First let's compute the complex function (output - input).
Such function is itself a function of the same complex frequency.
Its magnitude tells, at every jitter frequency, the amplitude of the sinusoidal distance between the output and the input phases. It is easy to realize that this function is the loop error function:

The phase error function is not very relevant in a pure PLL circuit, whose task is to track the input clock (and to dejitter it, maybe), but is extremely important if the PLL is serving into a CDR circuit.
The regeneration of the data depends on sampling the received pulses (that have undergone amplification, equalization and filtering of out-of-band noise) at a time when the remaining noise and intersymbol interference are not altering the pulse too much, close to the time of maximunm amplitude of that pulse. A significant phase error makes the probability of a wrong detection higher: in other words a phase error that is not affecting clock tracking may still increase to intolerable levels the bit error rate!
The following figure plots the magnitude of the error function. The y scale is in radian (1 radian ≈ 57.3°).
At low jitter frequencies there is practically no error, because the tracking is very good.
At very high jitter frequencies the error is practically identical to the input: in fact the PLL is not able to track the jitter and the local clock stays unmoving with respect to it.
At intermediate jitter frequencies, around fn, the error increases with frequency till it is as large as the input jitter itself, or even up to the point of becoming larger than it at frequencies just above fn for low values of ζ.
Large values of ζ ( >> 1) involve a large error even at frequencies much lower than fn, and small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above fn.
Values of ζ between 1.0 and 1.5 are therefore an inevitable design choice, but other considerations can be drawn from the study of the jitter tolerance function and suggest an even tighter range of ζ values for the CDR design.
It can be noted that both the jitter transfer and the jitter error functions are true "transfer functions". They tell the ratio of an output to an input (The function in the figure above can be easily seen as representing the magnitude of the error transfer function, and not just the error magnitude for an input of fixed, 1 radian, value). The function in the next sub section instead -the jitter tolerance function- is not a transfer function. In fact even the aspect of causality (that in a transfer function is the fact that the input generates the output) is not present. The jitter tolerance function describes the values of input jitter that generate a fixed value of phase error.
In real applications the PLL circuit will not operate correctly any more when the phase difference between input and ouptput (i.e. when the magnitude of the error funtion) exceeds a certain value that can be called φc. Depending on the PLL design, it may slip abruptly by the phase amount of one clock cycle, or it may exhibit other irregularities of operation. It is good design practice to have the φc value, in all jitter conditions, be larger than the error phase that the circuit is expected to tolerate. This situation of irregular operation is essentially encountered when the circuit non-linearities are reached. The next mathematical function, which corresponds also to a practical measurement condition for the circuit, is useful in describing the circuit behaviour when the boundaries of the non-linear operation are reached. This is the Jitter tolerance function, and is the subject of the next page.