Clock and data recovery/Structures and types of CDRs

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At the receiving end of a data transmission link, the received signal is amplified, filtered and equalized. Then a “slicer” circuit reshapes it and retains just the level transitions and the levels that represent the nominal values of the received signal in that interval between two consecutive transitions. The CDR functions are to process the “sliced” signal

• to extract the clock signal embedded in its transitions (clock recovery) and
• to sample and retime the pulses of the “sliced” signal(data recovery).

Clock recover circuits include:

• the phase locked loop architecture (PLL) -- the most common method of clock recovery
• the synchronous oscillator -- less common, but has some advantages over PLL^[1]

Many good books are available, with theory and practical examples, like^[2].
It is useful however, in order to get the best out of them, to have the ability to recognize in each case the fundamental architecture, that is the "Control Systems" model to refer to.

Contents 1 Importance of good reference models 2 Essential parts of a CDR 3 Order and type of a CDR 4 References

[edit] Importance of good reference models

The function of a CDR is a relatively simple one. The architectures possible for it are, accordingly, just a few, simple ones (actually just two!). It is nonetheless important to have a good knowledge of those architectures and a good understanding of their mathematical descriptions because these models are the best tools for the engineer that must deal with CDRs.

Starting from the definition and specification of (a communication system and of its) CDR(s), and all the way through all the different engineering tasks that logically follow like design, verification, validation, manufacturing tests, failure analysis, system operation and maintenance, those models can be an invaluable reference for the engineer. He will need them to imagine, specify, design, check, measure and interpret the behavior of a possible or of an existing CDR.

The actual implementation of the CDR may differ from the neat, simple analog structure that the mathematical model depicts. Complex digital blocks, DLLs, DSPs may render the analogy difficult to detect, but the fundamental signals and operation of the CDR can not differ. Yielding to the temptation of forgetting the models is a very risky and error prone short cut.

The essential signals and blocks of the model must be clearly identified in the actual system. The use of the reference model will be the best way to make sure that all aspects of the CDR operation are identified and taken into consideration.

The CDR is always designed with the architecture of a PLL (with the obvious addition of the regeneration block, where the received pulses are re-sampled with the local clock). Let’s study the PLL, that is the essential part. It should be kept in mind that such PLL will be specialized for application inside a CDR.

A PLL in a CDR is of unity feedback, of the first or of the second order and of type 1.

The PLLs inside CDRs are in all cases of the unity feedback kind. The input of the circuit is the phase of a reference signal (a clock or a serial data signal) and the output is the phase of a signal (a serial data stream or a simple clock). The output is locked -as much s the circuit can- to the input signal. The input signal is contrasted with the output signal in a phase comparator, whose output is the error signal. The error signal is processed and then used to control another circuit block that produces the output signal.

[edit] Essential parts of a CDR

It is important to identify the essential parts (listed below) of the CDR system but also to identify where the received signal and the local clock fit in the architecture. Either one (the received signal or the local clock) may act as input, while the other would simply act as an internal input signal inside the block called “Controlled element” (the block that generates the output signal of the PLL).

The received signal acts as reference input for the PLL when the PLL function is to generate a clock slaved to the received signal itself.
The local clock acts instead as reference signal for the PLL when the PLL function is simply to “phase align” the received signal to it, in the cases where the received signal timing is derived from the local clock itself (following a short loop inside a unique clock domain where the local clock is master).

The list of the parts that shall be clearly identified in the CDR are:

1. the phase information (carried by the level transitions) of the received signal
2. the phase information (carried by the level transitions) of the local clock
3. the phase comparator that measures the relative phase of the local clock with respect to the phase of (a signal related to) the received signal
4. an integration block (1/s in the language of Control Systems) or an accumulator if the implementation is of the discrete time type. It makes the control loop able to squeeze down to zero the steady state frequency error (and to a finite, small value the corresponding phase error)
5. the regeneration of (a signal related to) the received signal by the local clock.

[edit] Order and type of a CDR

The order of a control loop (causal, linear and time invariant in our models of CDRs) is the order of the differential equation that describes it.
In the language of control systems, the order is the number of poles of the (open or closed loop) system transfer function.

• 1st order systems are unconditionally stable, are characterised by one parameter only and are a good model to represent CDR PLLs that have been deliberately designed with a simple behaviour…….
• 2nd order systems are unconditionally stable, are characterised by two parameters and can be used to model practically all CDR PLLs for which the 1st order model is too simple.
• 3rd and higher order systems are not of practical use in the study of CDRs. They may be unstable in some conditions and ,moreover, they are more complex to use but do not offer a better behavior for CDR use than the 2nd order systems. ( Some complexity beyond the simple 2nd order system can be useful to model more accurately some parasitic effects of a CDR circuit, but not to design or to model performances in the range of functionality of the CDR).

The type of a control loop is the number of poles at the origin of the open loop transfer function (that is, how many times the factor 1/s appears in the open loop transfer function).
The type of a loop tells how well the loop itself is able to track a deviation of their input signal from the nominal value.
It should be reminded that a CDR can operate with a small phase (= sampling time) error without deterioration of performances, provided the error is small enough (a few degrees of jitter around the optimum sampling time do not deteriorate significantly the bit error rate!)

• Type 0 systems are able to track a step function ( a phase deviation of the input from the nominal phase expected by the circuit itself) with a small, but finite error. A type 0 PLL can not track at all a linear ramp of phase variation in the received signal (that is a step change of the frequency of the received signal with respect to the frequency of the -free running- local oscillator!). Therefore they are not of large use for CDRs.
• Type 1 systems are able to track signals that exhibit a step change of phase, without steady-state error. They are not able to track unit ramp inputs without a finite error, though.
  Type 1 system are the preferred type for CDRs, because they can be designed to phase lock:
  1. with zero phase error when there is no frequency (just phase) difference
  2. with a very small phase error when the master clock embedded in a received signal stream has a frequency different from the free running frequency of the local oscillator.
• Type 2 systems are not used in the study of CDRs because two poles in the open loop transfer function (in a unity feedback loop!) do not allow any margin for designing other needed performances of the PLL. Type 2 is incompatible with 1st order, and is also too much of a requirement for a 2nd order PLL with other useful characteristics.

[edit] References

1. ↑ "The Synchronous Oscillator" James A. Vincent, 1993
2. ↑ Behzad RAZAVI, Monolithic Phase-Locked Loops and Clock Recocvery Circuits .- Theory and Design. IEEE PRESS 1996 - ISBN 0-7803-1149-3