# Clock and Data Recovery/Noise is shaped by the PLL structure

#### What it is

In this page noise means phase noise, even when it can be traced back to voltage noise, current noise, limit cycles of a DSP, etc.
The signals have a fixed amplitude, and only their characteristic instants are affected by "instabilities": whatever noise spectral density is measured (or calculated) is phase noise[1] only. Phase noise is jitter (jitter is a "jittery" time difference) that is not present in the remote clock that has been used to transmit the data stream.
Either phase noise or jitter, their representation is a one-sided spectral density (where the clock (=carrier) frequency has disappeared) and the Fourier frequency ranges from 0 to ∞; nevertheless it includes fluctuations from both the upper and the lower sidebands of the clock[1].

It is common practice to separate the phase noise picked up by the incoming signal before it reaches the CDR (the "signal" phase noise)
from the additional phase noise that is generated by the CDR itself and that is present even when the input signal is practically noiseless (the "generated" phase noise).
See for instance [2].

• The "signal" noise comes from impairments (line distortions, line noise, receiver first stages, intersymbol interference, ..) suffered by the signal before it reaches the PLL input.
The PLL filters out the (high) frequencies of the jitter, because the true timing signal spectrum is known as to differ from the local clock only by a frequency offset and some low frequency wander.
This filtering action is modeled by the jitter transfer function.
• The "generated" noise is just the noise part that originates inside the CDR, and not the part that has been added to the signal along the preceding channel path.

The source of jitter that probably most often troubles practical circuits, is the one coming from supply noise inside the CMos circuitry of the CDR itself.
The internal supply rails inside an IC are affected by high current transients, that are generated inside output buffers, clock trees and other large CMos stages inside the IC itself, even if such blocks are not part of the CDR proper.
Those large current spikes will cause small ripple waves on the voltage supply lines.
Other CMos stages, inside the receive paths and inside the CDR proper, see –as a result of the supply ripples- their switching threshold ripple by exactly half the amount of the supply ripple.
The rise and fall edges of the waveforms inside these CMos stages are not perfectly steep, but exhibit a certain non negligible slope.
It is easy to see that a change of the CMOS threshold during the edge transition corresponds exactly to an earlier (or to a later) switching of the CMos stage: this time change, occurring almost at random at different transitions, will be nothing but a generated jitter.
It can be minimised (and should be minimised) by careful design and layout of the supply scheme inside the IC.

The other noise source that often is the origin of generated jitter inside the PLL is the VCO noise.

#### When it matters

Noise matters when its level is comparable with the signal level to the point that its presence affects the important characteristics of the signal.

In the CDR case, phase noise (=unwanted jitter) matters if it influences the Bit Error Rate (BER).
A good tutorial on how to measure, identify and possibly mitigate the unwanted jitter in a CDR is the Ransom Stephens Jitter Tutorial [3]

Many good books and papers address the CDR noise in general and the VCO noise (the main source of generated phase noise in actual CDRs) in particular. [4], [5], [6], [7], .

Focus here is made on the reshaping (transfer function) that a particular structure (of the three investigated in the following pages of this book: 1st order, type 1, 2nd order type 1 and 2nd order type 2) makes on the spectrum of the noise that is generated by the CDR circuitry itself.

As in previous and following pages, linear models of the three structures are used, but it will be suggested that the properties that the linear models identify are -to a good extent- present also in the non-linear variants of these structures.

#### Noise modeling

Noise is a "small signal" in the CDR, and can be studied with the linear models of the CDR blocks.

Noise may be injected at any node of a PLL, where only two nodes are significant: filter output and VCO output. (The node at the comparator output behaves the same as the PLL input, with the only difference of a flat gain Gφ)

In general, using the superposition principle, reference can be made to the following figures:

The phase noise generated inside each PLL block is modified before it appears at the PLL output,
block diagram and equations for the 2nd order type 1 loop
The phase noise generated inside each PLL block is modified before it appears at the PLL output,
block diagram and equations for the 2nd order type 2 loop.
Filter cut-off frequencies, damping ratios and natural undamped frequencies are chosen for a meaningful comparison.

The noise generated by the filter Nf is modified by the transfer equation TFNf = (TFfilter) / 1 + TFfilter*TFVCO)
The noise generated by the VCO No is modified by the transfer equation TFNo = 1/(1 + TFfilter*TFVCO)

#### How the PLL structure reshapes the noise spectrum

VCO noise - transfer functions VCO-to-output of the loops of order 1 type 1, order 2 type 1 and order 2 type 2.
Filter cut-off frequencies, damping ratios and natural undamped frequencies are chosen for a meaningful comparison.

The curves in the above figure can be redrawn, with different parameter values, using the same OpenOffice.org[1] Calc spreadsheet that was used to create them.

PLL 11 21 22 linear small signal models of Jitter transfer, error, tolerance and noise Rev 1.0 August 13 2011

#### Summing up

The VCO noise is the most important to consider, because the VCO produces low frequency noise and those low frequency components can not be distinguished from the useful signal components of the same frequencies.

All loop models act as high-pass for the VCO noise, i.e. they mitigate the low frequency noise from the VCO.

The high-pass corner frequency coincides with their natural frequency.

All loops therefore tend to reject the low frequency noise that is generated by the VCO, but with some differences:

• the 1 - 1 loop attenuates the VCO noise at all frequencies below $\omega_{1}$, with a single slope (20 dB/decade) and no gain overshoot. All VCO noise components at frequencies higher than $\omega_{1}$ appear unmodified in the PLL output.

• the 2 - 1 loop attenuates the VCO noise at all frequencies below $\omega_{21}$, with a single slope (20 dB/decade) and with a gain overshoot that - whenever ζ > 0 , i.e. always - peaks at $\tfrac{\omega^2}{\omega_{n21}^2} = \tfrac{1 + \sqrt{1+8\zeta_{21}^{2}}}{2}$ reaching a peak value that can represent a problem whenever ζ21 is lower than 0.5.
The following figure illustrates the behavior of the 1-1 and 2-1 loops (using on purpose for the 2-1 a damping ratio that is unacceptably low) and gives the relevant formulas.
VCO to output (noise) transfer functions of the PLLs of order 1 type 1 and order 2 type 1, as well as the transfer function of the filter block for the order 2 loop.
The damping ratio of the 2nd order loop has been chosen too low on purpose, to emphasize the risk of amplification of noise at certain frequencies.
The 2-1 loop is normally used in regenerator applications (when $\omega_{21}$ is low): a low noise VCO must be used.
It also needs very good control of ζ21 that must be kept close to 1.0 (this rules out the use of blocks with hard non-linearities and largely variable gain, like bang-bang phase detectors).

• the 2 - 2 loop attenuates the VCO noise at all frequencies below $\omega_{22}$, with a double slope (40 dB/decade).
There can be noise amplification at certain frequencies because of the gain magnitude oveshoots 0 dB, whenever $\zeta_{22}$1/2 .
The peaking of the overshoot occurs at ω = ω22 / 1 − 2ζ², and reaches as high as 20log10(1 / (2ζ1 − 2ζ²)).
The following figure illustrates the behavior of the 1-1 and 2-2 loops (using on purpose for the 2 - 2 a damping ratio that is unacceptably low) and gives the relevant formulas.
VCO to output (noise) transfer functions of the PLLs of order 1 type 1 and order 2 type 2, as well as the transfer function of the filter block for the order 2 loop.
The damping ratio of the 2nd order loop has been chosen too low on purpose, to emphasize the risk of amplification of noise at certain frequencies.
The 2-2 loop is a good choice if a noisy VCO must be used and is certainly preferable when some loop parameters can vary in a wide range because of hard non linearities (if G can become very large in certain conditions e.g. when a bang-bang detector is used)).

This architecture is the best of the three to mitigate a noisy VCO (see the double slope of attenuation for low frequencies), but the damping ratio $\zeta_{22}$ shall remain larger than 1/2 = 0.707, to avoid amplification of noise frequencies around ω22.

### External References

1. a b IEEE Std 1139-1999 IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology—Random Instabilities, http://www.umbc.edu/photonics/Menyuk/Phase-Noise/Vig_IEEE_Standard_1139-1999%20.pdf
2. Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino, “A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's” from IEEE Journal of Solid-State Circuits, June 1999
3. Ransom Stephens, “Tektronics Jitter 360° Knowledge Series” from http://www.tek.com/learning/
4. Leeson, D. B. (February 1966), "A Simple Model of Feedback Oscillator Noise Spectrum", Proceedings of the IEEE 54 (2): 329–330, doi:10.1109/PROC.1966.4682
5. Noise Properties of PLL Systems, by Venceslav F. Kroupa, in IEEE Trans. Comm., vol. COM-30, pp. 2244-2252, October 1982.
6. A General Theory of Phase Noise in Electrical Oscillators, by Ali Hajimiri and Thomas H. Lee, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 http://www.chic.caltech.edu/Publications/general_full.PDF