360 Assembly/360 Architecture
The 360 architecture is a 32-bit machine, in which the standard word size is 32 bits.
The 360 architecture has:-
- 16 general purpose 32-bit registers, 0 to 15 (usually Equated to the labels "R0" through "R15")
- 16 privileged 32-bit control registers, 0 to 15, used to control various operations of the computer
- 4 floating point 64-bit registers numbered 0, 2, 4 and 6, and
- a 64-bit Program Status Word (PSW). The program status word is composed of the privileged bit, the program counter, and the memory protection key.
The privileged bit indicates the state of the program that is currently executing. There are two states, problem and supervisor. A program is in supervisor state if the privileged bit is set.
- Problem state is where all user software operates. Problem state applications have restrictions including memory read and write restrictions, and cannot directly issue I/O instructions.
- Supervisor state is reserved for the operating system and any of its components.
The memory protection key is 4 bits and determines which memory areas the particular program has access to. Pages of the computer's memory are marked with certain protection keys, and only a program running with the same key (or key of zero) may write to a particular section of memory.
Certain registers on the 360 are "reserved" either by hardware requirements, or by convention.
Register 0 is generally used in a number of instructions as a placeholder to indicate a lack of action. Many (non-RR) instructions treat use of register 0 as having no value (equivalent to low storage - address X'00000000' in memory - which is usually protected unless operating in supervisor state.)
Register 1 is, by convention, used to point to the list of arguments (32 bit addresses) passed to a called subroutine, and for passing arguments for operating system calls (SVC's). It is also used by the Translate and Test instruction TRT specifically.
Register 2 may be used by some instructions for additional parameters or return values.
Register 13 is, by convention, used to point to a save area for storing the passed registers by a called subroutine. It is the logical equivalent of a "stack pointer" on processors that have a stack.
Register 14 is, by convention, used to provide the address for a called subroutine to return to the caller.
Register 15 is, by convention, used to provide the entry point address of a called subroutine and to provide the initial base register for the subroutine. The subroutine may continue to use register 15 as its base register if it is short (and doesn't itself call a lower level subroutine) or, more typically, it will save this register (and others) immediately in the provided save area and use a different register (or set of registers) for the base. Also, register 15 may be used by some operating systems to provide some arguments for SVC's. Its use for this purpose bears some similarity to the Program Counter register on some mini and microcomputers. Register 15, by convention, is also frequently used as a return value from called subroutines, often set to an index value (0,4,8,12 etc.), suitable for direct use in a branch table immediately after return.
The Program Status Word (PSW) is a 64-bit privileged register which contains information about the current state of the machine. Privileged programs can change the contents of the entire PSW through the LPSW privileged instruction. Non-privileged programs may change some bits in the PSW through execution of various instructions including the SVC instruction, or through certain arithmetic and comparison instructions, as well as via branch instructions. Sections of the PSW which have fixed values are shown in the table below in green.
An explanation of the fields in the PSW is as follows.
- (R) - Bit 1: Set to allow Program Event Recording (PER) interrupts if certain PER event-mask bits are set in Control Register 9.
- (T) - Bit 5: Set if Dynamic Address Translation (DAT) is enabled; this allows for virtualization of addresses.
- (IO) - Bit 6: Set if Input/Outpit (IO) interrupts can occur, controlled by bits in Control Register 6.
- (EX) - Bit 7: Set if external interrupts can occur.
- (Key) - Bits 8-11: Contains the storage key for the current running task. This key is 0 for privileged tasks. A task may only access areas of memory which are marked with the same key unless its key is 0.
- (M) - Bit 13: Set if a Machine Check interrupt is permitted to occur in the event of detection of damage. Subject to mask bits set in Control Register 14.
- (W) - Bit 14: Set if the machine is in wait state, clear if the machine is running.
- (P) - Bit 15: Set if the machine is in supervisor state, clear if the machine is in problem state.
- (AS)- Bits 16 and 17: Used in combination with the T-bit to control how address translation is to be performed.
- (CC)- Bits 18 and 19: Condition Code, used to indicate the results of an arithmetic, comparison or logical instruction.
- (Prog Mask) - Bits 20-23: Indicates if certain arithmetic exceptions are masked against causing an interrupt. These masks are
- Bit 20 - Integer overflow
- Bit 21 - Decimal overflow
- Bit 22 - Floating-point underflow
- Bit 23 - Floating-point overflow
- (A) - Bit 32: Set if 31-bit addressing is enabled; clear if 24-bit addressing is in use.
- (Instruction Address)- Bits 33-63: 24-bit (or 31-bit if A-bit is set) address of the current instruction being executed.
|360 Assembly Language|
|360 Family||Introduction · Basic FAQ · 360 Family · 360 Architecture · Comments|
|360 Instruction Set||360 Instructions · Branch Instructions · Data Transfer Instructions · Control Flow Instructions · Arithmetic Instructions · Logic Instructions · Shift and Rotate Instructions · Other Instructions|
|Syntaxes and Assemblers||360 Assemblers· Pseudo Instructions|
|Instruction Extensions||Floating Point · High-Level Languages|